1. Field of the Invention
The present invention relates to a semiconductor memory device and its production process and, more particularly, to a semiconductor memory device provided with a memory transistor having a charge storage layer and a control gate, and its production process.
2. Description of the Related Art
As a memory cell of an EEPROM, there is known a device of a MOS transistor structure having a charge storage layer and a control gate in a gate portion, in which an electric charge is injected into and released from the charge storage layer by use of a tunnel current. In this memory cell, data “0” and “1” is stored as changes in a threshold voltage according to the charge storing state of the charge storage layer.
For example, in the case of an n-channel memory cell using a floating gate as the charge storage layer, when a source/drain diffusion layer and a substrate are grounded and a high positive voltage is applied to the control gate, electrons are injected from the substrate into the floating gate by a tunnel current. This injection of electrons shifts the threshold voltage of the memory cell to be positive. When the control gate is grounded and a high positive voltage is applied to the source/drain diffusion layer or the substrate, electrons are released from the floating gate to the substrate by the tunnel current. This release of electrons shifts the threshold voltage of the memory cell to be negative.
In the above-described operation, a relationship of capacity coupling between the floating gate and the control gate with capacity coupling between the floating gate and the substrate plays an important role in effective injection and release of electrons, i.e., effective writing and erasure. That is, the larger the capacity between the floating gate and the control gate is, the more the potential of the control gate can be transmitted effectively to the floating gate and the easier the writing and erasure become.
With recent development in semiconductor technology, especially, in micro-patterning techniques, the size reduction and the capacity increase of memory cells of EEPROM are rapidly progressing.
Accordingly, it is an important issue to assure a large capacity between the floating gate and the control gate without enlarging the memory cell area.
For increasing the capacity between the floating gate and the control gate, it is necessary to thin a gate insulating film therebetween, to increase the dielectric constant of the gate insulating film or to enlarge an area where the floating gate opposes the control gate.
However, the thinning of the gate insulating film is limited in view of reliability of memory cells. In order to increase the dielectric constant of the gate insulating film, for example, a silicon nitride film is used as the gate insulating film instead of a silicon oxide film. This is also questionable in view of reliability and is not practical.
Therefore, in order to ensure a sufficient capacity between the floating gate and the control gate, it is necessary to set a sufficient overlap area therebetween. This is, however, contradictory to the size reduction of memory cells and the capacity increase of EEPROM.
In an EEPROM disclosed by Japanese Patent No. 2877462, memory transistors are formed by use of sidewalls of a plurality of columnar semiconductor layers arranged in matrix on a semiconductor substrate, the columnar semiconductor layers being separated by trenches in a lattice form.
FIG. 238 shows the EEPROM. FIG. 238 is a plan view of the EEPROM in which columnar silicon layers 2 are cylindrical, that is, the top face has a circular shape. FIGS. 239A and 239B are sectional views taken on lines A–A′ and B–B′, respectively, in FIG. 238. In FIG. 238, selection gate lines formed by continuing gate electrodes of selection gate transistors are not shown for avoiding complexity of the figure.
The EEPROM uses a P-type silicon substrate 1, on which a plurality of columnar P-type silicon layers 2 are arranged in matrix. The columnar P-type silicon layers 2 are separated by trenches 3 in a lattice form and each of the columnar silicon layers 2 functions as a memory cell region. The memory transistor is constructed by drain diffusion layers 10 formed on the top of the silicon layers 2, common source diffusion layers 9 formed at the bottom of the trenches 3, floating gates 6 formed below the silicon layers 2 with intervention of tunnel oxide films 5 so as to surround the silicon layers 2, and control gates 8 formed with intervention of interlayer insulating films 7 on the outside of the floating gates 6. Oxide films 4 are buried at the bottom of the trenches 3. As shown in FIGS. 238 and 239B, the control gates 8 are provided continuously for a plurality of memory cells in one direction so as to form control gate lines or word lines WL (WL1, WL2, . . . ). In a direction crossing the control gate line, bit lines connected to the drain diffusion layers of the plurality of memory transistors are provided.
In a one transistor/one cell structure, if a memory transfer is over-erased (specifically, a reading potential is 0 V and the threshold is negative), a cell current flows in the memory cell even if the cell is not selected and it is inconvenient. In order to surely prevent it, like the memory transistors, selection gate transistors are formed by providing gate electrodes 32 around an upper part of the silicon layers 2 with intervention of gate oxide films 31. The gate electrodes 32 of the transistors, like the control gates 8 of the memory cells, are provided continuously in the same direction as that of the control gate lines to form selection gate lines.
In the control gate lines, a mask by PEP is formed in columnar silicon layer positions at ends of the cell array. Contact portions 14 made by a polysilicon layer continued from the control gate lines are left on the surface. Also in the selection gate lines, contact portions 15 are left on silicon layers on an end opposite to the contact portions 14 of the control gates. Aluminum wires 13 and 16 to become control gate lines CG and the word lines WL, respectively, are in contact with the contact portions 14 and 15, respectively.
The surface of the substrate of the memory cells formed as described above is covered with a CVD oxide film 11. In the CVD oxide film 11, contact holes are opened, and aluminum wires 12 are provided which serve as bit lines BL (BL1, BL2, . . . ) for connecting the drain diffusion layers 10 of memory cells lined in a direction crossing the word lines WL.
With such a configuration, sufficiently large capacitance between the charge storage layer and the control gate can be assured with a small occupation area. The drain diffusion layers connected to the bit lines of memory cells are formed on the top of the columnar semiconductor layers and are electrically completely insulated by trenches. The device isolation area can be reduced, so that a small memory cell size is achieved. Therefore, a larger-capacity EEPROM in which memory cells having excellent writing and erasing efficiency are integrated can be obtained.
A concrete production process of the EEPROM shown in FIG. 239A will be described with reference to FIGS. 240A to 240G.
The P-type silicon layer 2 with a low impurity concentration is epitaxially grown on the P-type silicon substrate 1 (wafer) with a high impurity concentration. A mask layer 21 is deposited on the silicon layer 2 and a photoresist pattern 22 is formed by a known PEP process. The mask layer 21 is etched by using the photoresist pattern 22 (FIG. 240A).
The silicon layer 2 is etched by a reactive ion etching method using the resulting mask layer 21 to form the trenches 3 in a lattice form which reach the substrate 1. Thereby the silicon layer 2 is separated into a plurality of columnar islands. A silicon oxide film 23 is deposited by a CVD method and anisotropically etched to remain on the sidewalls of the columnar silicon layers 2. By implantation of N-type impurity ions, the drain diffusion layers 10 are formed on the top of the columnar silicon layers 2. The common source diffusion layers 9 are formed at the bottom of the trenches (FIG. 240B).
The oxide films 23 around the columnar silicon layers 2 are etched away by isotropic etching. Channel ion implantation is carried out on the sidewalls of the columnar silicon layers 2 by use of a slant ion implantation as required. By the CVD method instead of the channel ion implantation, an oxide film containing boron may be deposited and diffusion of boron from the oxide film may be utilized. The silicon oxide film 4 is deposited by the CVD method and isotropically etched to be buried at the bottom of trenches 3. The tunnel oxide films 5 are formed to a thickness of about 10 nm around the silicon layers 2 by thermal oxidation. A first-layer polysilicon film is deposited on the tunnel oxide films 5 and is anisotropically etched while leaving the film on lower sidewalls of the columnar silicon layers 2, thereby forming the floating gates 6 around the silicon layers 2 (FIG. 240C).
The interlayer insulating films 7 are formed on the surface of the floating gates 6 formed around the columnar silicon layers 2. The interlayer insulating film 7 is an ONO film, for example. A second-layer polysilicon film is deposited on the interlayer insulating films 7 and is anisotropically etched to form the control gates 8 on lower parts of the columnar silicon layers 2 (FIG. 240D). At this time, the control gates 8 are formed as control gate lines continuous in a longitudinal direction in FIG. 238 without using a masking process by pre-setting intervals between the columnar silicon layers 2 in the longitudinal direction at a predetermined value or less. Unnecessary parts of the interlayer insulating films 7 and underlying tunnel oxide films 2 are etched away. A silicon oxide film 111 is deposited by a CVD method and etched halfway down the trenches 3, that is, to a depth such that the floating gates 7 and control gates 8 of the memory cells are buried and hidden (FIG. 240E).
The gate oxide film 31 is formed to a thickness of about 20 nm on the exposed parts of the columnar silicon layers 2 by thermal oxidation. A third layer polysilicon film is deposited and anisotropically etched to form the gate electrodes 32 of MOS transistors (FIG. 240F). The gate electrodes 32 are also patterned to be continuous in the same direction as the control gate lines, thereby forming selection gate lines. The selection gate lines can be formed continuously in self-alignment, but this is more difficult than the control gates 8 of the memory cells. For, the selection gate transistors are single-layer gates whereas the memory transistors are two-layered gates, and therefore, the intervals between gate electrodes of adjacent cells are wider than the intervals between the control gates. Accordingly, in order to ensure that the gate electrodes 32 are continuous, the gate electrodes may be formed in a two-layer polysilicon structure, a first polysilicon film may be patterned to remain only in locations to connect the gate electrodes by use of a masking process, and a second polysilicon film may be left on the sidewalls of the columnar silicon layers 2.
The control gate lines and selection gate lines are covered with a mask before corresponding polysilicon film etching so that the contact portions 14 and 15 are formed on the top of the columnar silicon layers at different ends.
Finally, a silicon oxide film 112 is deposited by a CVD method and, as required, is planarized. Contact holes are opened and an Al film is deposited and patterned to form Al wires 12 to be bit lines BL, aluminum wires 13 to be control gate lines CG and aluminum wires 16 to be word lines WL at the same time (FIG. 240G).
FIG. 241A is a schematic sectional view of a major part of one memory cell of the EEPROM, and FIG. 241B shows an equivalent circuit of the memory cell. The operation of the EEPROM will be briefly explained with reference to FIGS. 241A and 241B.
For writing by use of injection of hot carriers, a sufficiently high positive potential is applied to a selected word line WL, and predetermined positive potentials are applied to a selected control gate line CG and a selected bit line BL. Thereby, a positive potential is transmitted to the drain of a memory transistor Qc via a selected gate transistor Qs to let a channel current flow in the memory transistor Qc and inject hot carriers. Thereby, the threshold of the memory cell is shifted to be positive.
Data is erased by applying 0 V to a selected control gate CG and applying high positive potentials to the word line WL and the bit line BL to release electrons from the floating gate to the drain. Data in all the memory cells is erased by applying a high positive potential to the common sources to release electrons to the sources. Thereby, the thresholds of the memory cells are shifted to be negative.
Data is read by rendering the selection gate transistor Qs to be ON by the word line WL and applying a reading potential to the control gate line CG. Whether data is “0” or “1” is determined according to the presence or absence of a current.
In the case where the Fowler-Nordheim tunneling is utilized for injecting electrons, high potentials are applied to a selected control gate line CG and a selected word line WL and 0 V is applied to a selected bit line BL to inject electrons from the substrate to the floating gate.
In this EEPROM, the control gates of the memory cells are formed to be continuous in one direction without using a mask. This is possible, however, only when the columnar silicon layers are not arranged symmetrical. That is, by setting the intervals between adjacent columnar silicon layers in a word line direction to be smaller than the intervals between adjacent columnar silicon layers in a bit line direction, it is possible to automatically obtain control gate lines that are separated in the bit line direction and are continuous in the word line direction without using a mask.
In contrast, when the columnar silicon layers are arranged symmetrically, a PEP process is required. More particularly, the second-layer polysilicon film is deposited thick, and through the PEP process, the second-layer polysilicon film is selectively etched to remain in locations to be continuous as control gate lines. The third-layer polysilicon film is deposited and etched to remain on the sidewalls as described above. Even in the case where the columnar silicon layers are arranged asymmetrically, there is a case such that the continuous control gate lines cannot be automatically formed depending upon the intervals of the columnar silicon layers. In such a case as well, it is sufficient to form the control gate lines continuous in one direction by using the mask process as described above. Although the memory cells of the floating gate structure is used in the EEPROM, the charge storage layers do not have to have the floating gate structure but may have a structure such that the charge storage layer is realized by a trap in a laminated insulating film, e.g., a MNOS structure.
FIG. 242 is a sectional view of a memory cell of the MNOS structure. FIG. 242 corresponds to FIG. 239A.
A laminated insulating film 24 functioning as the charge storage layer is has a laminated structure of a tunnel oxide film and a silicon nitride film, or has a structure in which a tunnel oxide film, a silicon nitride film and further an oxide film are stacked.
FIG. 243 is a sectional view of a conventional EEPROM in which the memory transistors and the selection gate transistors are exchanged, specifically, the selection gate transistors are formed in the lower parts of the columnar silicon layers 2 and the memory transistors are formed in the upper parts of the columnar silicon layers 2. FIG. 243 corresponds to FIG. 239A. This structure in which the selection gate transistors are provided on a common source side can apply to the case where the injection of hot electrons is used for writing.
FIG. 244 shows an example in which a plurality of memory cells are formed on one columnar silicon layer. The same numbers are given to components corresponding to those in the above-described examples and their description will not be repeated.
In this EEPROM, a selection gate transistor Qs1 is formed in the lowermost part of a columnar silicon layer 2, three memory transistors Qc1, Qc2 and Qc3 are laid above the selection gate transistor Qs1, and another selection gate transistor Qs2 is formed above.
In the above example, however, as shown in FIG. 241A, diffusion layers do not exist between the selection gate transistors Qs and the memory transistors Qc. This is because, it is hard to form the diffusion layers selectively on the sidewalls of the columnar silicon layers.
Therefore, in the structure shown in FIGS. 239A and 239B, desirably, isolation oxide films between the gates of the memory transistors and the gates of the selection gate transistors are as thin as possible. In the case of utilizing the injection of hot electrons, in particular, the thickness of the isolation oxide films has to be about 30 to 40 nm for allowing a sufficient “H” level potential to be transmitted to the drain of a memory transistor.
Such fine intervals, however, cannot be practically made only by burying the oxide films by the CVD method as described in the above production process.
In the above example, transistors are formed in a direction vertical to the substrate stage by stage, so that it causes increase in the number of the production steps, increase in the manufacturing cost, increase in manufacturing period and deterioration in the yield. In the produced memory transistor, characteristics of the memory cells vary owing to differences in the properties of the tunnel oxide films caused by thermal histories different stage by stage, and differences in the profile of diffusion layers.
Further, although the charge storage layer and the control gate are formed in self-alignment with the columnar semiconductor layer in the example, from the viewpoint of increase in the capacity of the cell array, it is preferable to form the columnar semiconductor layer with the minimum processing dimensions. In the case of using the floating gate as the charge storage layer, the relation between capacitive coupling between the floating gate and the control gate and capacitive coupling between the floating gate and the substrate is determined by the area of the periphery of the columnar semiconductor layer, the area of the periphery of the floating gate, thickness of the tunnel oxide film for insulating the columnar semiconductor layer from the floating gate, and thickness of the interlayer insulating film for insulating the floating gate from the control gate. In the above example, an object is to provide a charge storage layer and a control gate formed around the columnar semiconductor layer by using the side walls of the columnar semiconductor layer and to assure sufficiently large capacitance between the charge storage layer and the control gate with the small occupation area. In the case of forming the columnar semiconductor layer with the minimum processing dimensions and the thickness of the tunnel oxide film and the thickness of the interlayer insulating film are fixed, the capacitance between the charge storage layer and the control gate is simply determined by the area of the periphery of the floating gate, that is, the thickness of the floating gate. Therefore, it is difficult to further increase the capacitance between the charge storage layer and the control gate without increasing the occupation area of the memory cell. In other words, it is difficult to increase the ratio of the capacitance between the floating gate and the control gate to the capacitance between the floating gate and the island-like semiconductor layer without increasing the occupation area of the memory cell.
In the above example, if a plurality of memory cells are connected in series on one columnar semiconductor layer and the thresholds of the memory cells are supposed to be the same, significant changes take place in the thresholds of memory cells at both ends of the memory cells connected in series owing to a back-bias effect of the substrate in a reading operation. In the reading operation, the reading potential is applied to the control gate lines CG and “0” or “1” is determined according to the presence or absence of a current. For this reason, the number of memory cells connected in series is limited in view of the performance of memories. It is therefore to realize further increase in capacity.